US 11,698,772 B2
Prepare for shorter precision (round for reround) mode in a decimal floating-point instruction
Eric Mark Schwarz, Gardiner, NY (US); and Martin Stanley Schmookler, Austin, TX (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 21, 2020, as Appl. No. 17/26,407.
Application 17/026,407 is a continuation of application No. 16/550,257, filed on Aug. 25, 2019, granted, now 10,782,932.
Application 16/550,257 is a continuation of application No. 16/185,028, filed on Nov. 9, 2018, granted, now 10,423,388, issued on Sep. 24, 2019.
Application 16/185,028 is a continuation of application No. 15/852,180, filed on Dec. 22, 2017, granted, now 10,127,014, issued on Nov. 13, 2018.
Application 15/852,180 is a continuation of application No. 15/470,692, filed on Mar. 27, 2017, granted, now 9,851,946, issued on Dec. 26, 2017.
Application 15/470,692 is a continuation of application No. 14/943,254, filed on Nov. 17, 2015, granted, now 9,690,544, issued on Jun. 27, 2017.
Application 14/943,254 is a continuation of application No. 13/848,885, filed on Mar. 22, 2013, granted, now 9,201,846, issued on Dec. 1, 2015.
Application 13/848,885 is a continuation of application No. 11/680,894, filed on Mar. 1, 2007, granted, now 8,443,029, issued on May 14, 2013.
Prior Publication US 2021/0004206 A1, Jan. 7, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/499 (2006.01); G06F 9/30 (2018.01); G06F 7/491 (2006.01); G06F 7/483 (2006.01); G06F 17/10 (2006.01); G06F 7/38 (2006.01)
CPC G06F 7/49957 (2013.01) [G06F 7/386 (2013.01); G06F 7/483 (2013.01); G06F 7/491 (2013.01); G06F 7/49915 (2013.01); G06F 7/49963 (2013.01); G06F 7/49968 (2013.01); G06F 7/49973 (2013.01); G06F 7/49978 (2013.01); G06F 7/49984 (2013.01); G06F 9/30014 (2013.01); G06F 17/10 (2013.01); H05K 999/00 (2013.01); H05K 999/99 (2013.01); G06F 7/49947 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A computer implemented method for indicating with any least significant decimal coefficient digit of 0 or 5 that a result of a rounding of a decimal floating-point (DFP) number to a lesser precision in a computer processor is an exact (precise) result, the method comprising:
fetching a DFP round-for-reround instruction in a machine, the machine implementing a plurality of floating point registers and including the computer processor:
executing, by the computer processor, the DFP round-for-reround instruction in a round-for-reround mode, wherein the DFP round-for-reround instruction is configured to perform a DFP operation on a DFP operand, the executing the DFP round-for-reround instruction comprising:
based on being in the round-for-reround mode, forming, by the computer processor, from a decimal coefficient number having a high order portion and a low order portion, an intermediate result from the high order portion, wherein the intermediate result has a least significant decimal coefficient digit;
without changing any coefficient digit of the intermediate result, other than the least significant decimal coefficient digit, creating from the intermediate result a rounded-for-reround DFP number, the creating comprising:
based on the least significant coefficient digit of the intermediate result being 0 or 5 and based on the low order portion having any value other than 0, incrementing the least significant coefficient digit of the intermediate result; and
storing in computer processor storage, by the computer processor, the intermediate result as a final result of the executed DFP operation, wherein the intermediate result is the rounded-for-reround DFP number, wherein a final result having a least significant digit of 0 or 5 indicates that the final result is exact and that the low order portion is 0, wherein a final result having a least significant digit of any one of 1, 2, 3, 4, 6, 7, 8 and 9 does not indicate that the final result is exact and does not indicate that the low order portion is 0.