US 11,698,751 B2
Data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer
Dinesh Kumar Agarwal, Karnataka (IN); and Amit Sharma, Karnataka (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jun. 7, 2021, as Appl. No. 17/340,399.
Prior Publication US 2022/0391132 A1, Dec. 8, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a volatile memory;
a non-volatile memory; and
a controller configured to:
store data in a host memory buffer in a host;
maintain dual copies of updates to the data in both the host memory buffer and the volatile memory in the data storage device until a number of updates exceeds a threshold after which updates are stored in the host memory buffer without storing copies of the updates in the volatile memory in the data storage device;
receive information from the host that a first area of the host memory buffer will not be powered on during a low-power state;
identify update(s) stored in the first area of the host memory buffer that do not have copies stored in the volatile memory in the data storage device; and
prior to the host entering the low-power state, flush the identified update(s) from the first area of the host memory buffer to a second area of the host memory buffer that will be powered on during the low-power state.