| US 11,698,750 B2 | ||
| Smart re-use of parity buffer | ||
| Bhanushankar Doni, Bangalore (IN); and Pratik Bhatt, Ahmedabad (IN) | ||
| Assigned to SanDisk Technologies LLC, Addison, TX (US) | ||
| Filed by SanDisk Technologies LLC, Addison, TX (US) | ||
| Filed on Oct. 4, 2021, as Appl. No. 17/492,983. | ||
| Prior Publication US 2023/0112636 A1, Apr. 13, 2023 | ||
| Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01) | ||
| CPC G06F 3/0656 (2013.01) [G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 11/1004 (2013.01)] | 20 Claims |
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1. An apparatus comprising:
volatile memory; and a control circuit coupled to the volatile memory, the control circuit configured to communicate with a plurality of non-volatile memory cells, the control circuit configured to:
program user data into a first group of the plurality of non-volatile memory cells;
accumulate primary parity for the user data in a buffer of the volatile memory;
replace a first unit of the primary parity in a first portion of the buffer with data other than primary parity while a second portion of the buffer is still being used to store a second unit of the primary parity; and
store a final accumulation of the primary parity in the buffer to a second group of the plurality of non-volatile memory cells.
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