CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |
1. A memory system comprising:
a plurality of memory devices including a plurality of blocks configured of memory cells; and
a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices,
wherein the memory controller is further configured to:
open a target zone among the plurality of zones in response to a request from outside,
determine an offset of the target zone based on one or more selected from the group consisting of order in which the target zone is opened among the plurality of zones, ready-busy signals received from the plurality of memory devices, and erase counts of the plurality of blocks; and
determine a logical address of the target zone on which a write operation is to be started based on the offset and a write pointer corresponding to the target zone.
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