CPC G06F 3/0631 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
a main memory comprising a front end electronics (FME) circuit and memory cells arranged on dies arranged as die sets accessible using parallel channels; and
a controller configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among the commands responsive to the occurrence rate of the collisions, the controller further configured to divide a selected command into at least a first partial command and a second partial command so that the first partial command utilizes a first set of resources that are currently available and the second partial command utilizes a second set of resources that are not currently available, the controller further configured to forward the first partial command to the main memory responsive to the first set of resources being currently available and subsequently forward the second partial command to the main memory responsive to the second set of resources becoming subsequently available, the controller further comprising a command scheduler configured to respectively direct the commands to the FME circuit in an order responsive to availability of the resources and responsive to the ratio.
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