CPC G06F 1/12 (2013.01) [G06F 1/06 (2013.01); H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
a plurality of clock generators configured to respectively generate a plurality of clock signals;
a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals; and
controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one of the plurality of clock generators so that the at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.
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