US 11,698,659 B2
Integrated circuit and operating method thereof
Jieun Ahn, Seongnam-si (KR); Sungcheol Park, Seoul (KR); and Kiseok Bae, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 22, 2021, as Appl. No. 17/559,255.
Claims priority of application No. 10-2021-0025964 (KR), filed on Feb. 25, 2021.
Prior Publication US 2022/0269306 A1, Aug. 25, 2022
Int. Cl. H03K 3/00 (2006.01); G06F 1/12 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); G06F 1/06 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/06 (2013.01); H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of clock generators configured to respectively generate a plurality of clock signals;
a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals; and
controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one of the plurality of clock generators so that the at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.