CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); H03K 5/00006 (2013.01); H03K 2005/00286 (2013.01); H04B 1/04 (2013.01)] | 20 Claims |
1. A communication circuit, comprising:
a clock input;
a clock divider circuit configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, wherein N is an integer, and wherein the clock divider circuit is configured to:
generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal,
generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, wherein the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and
generate the output clock signal based at least in part on the 2N unique phase shifted clock signals; and
a mixer, configured to receive the output clock signal.
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