CPC G05F 3/20 (2013.01) [H03L 1/00 (2013.01)] | 16 Claims |
1. A system, comprising:
a first stage having a current bias generator that generates a biasing current, the current bias generator including a resistor structure that comprises an emulated resistor;
a second stage coupled to the first stage, wherein the second stage has a load that utilizes the biasing current generated by the current bias generator; and
a reference voltage generator that generates a reference voltage,
wherein the reference voltage generator includes a first native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
wherein the first native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
wherein the reference voltage is used to activate the second plurality of stacking transistor structures.
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