US 12,356,875 B2
RRAM bottom electrode
Fu-Chen Chang, New Taipei (TW); Kuo-Chi Tu, Hsin-Chu (TW); and Wen-Ting Chu, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 4, 2024, as Appl. No. 18/732,725.
Application 18/732,725 is a continuation of application No. 17/533,411, filed on Nov. 23, 2021, granted, now 12,041,861.
Application 17/533,411 is a continuation of application No. 16/395,620, filed on Apr. 26, 2019, granted, now 11,189,788, issued on Nov. 30, 2021.
Claims priority of provisional application 62/752,593, filed on Oct. 30, 2018.
Prior Publication US 2024/0324478 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/841 (2023.02) [H10N 70/063 (2023.02); H10B 63/30 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate;
a memory cell formed over the substrate, the memory cell comprising a bottom electrode, a dielectric layer, and a top electrode;
wherein the bottom electrode comprises a bulk region having a composition and an interfacial region that is within the bottom electrode and has the same composition as the bulk region;
the interfacial region forms an interface with the dielectric layer; and
the composition has a higher density within the interfacial region than the composition in the bulk region.