US 12,356,874 B2
Semiconductor device and method of manufacturing semiconductor device
Jun Ku Ahn, Icheon (KR); Gwang Sun Jung, Icheon (KR); Jong Ho Lee, Icheon (KR); and Uk Hwang, Icheon (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Jul. 21, 2021, as Appl. No. 17/382,057.
Claims priority of application No. 10-2021-0017026 (KR), filed on Feb. 5, 2021.
Prior Publication US 2022/0254997 A1, Aug. 11, 2022
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/826 (2023.02) [H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first electrode;
a second electrode;
an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall;
a variable resistance layer formed in the opening, the variable resistance layer including a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area; and
a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode,
wherein the variable resistance layer is programmed by performing a program operation to store logic states corresponding to a first amorphous state having a first resistance and a second amorphous state having a second resistance lower than the first resistance,
wherein the insulating layer comprises:
a first insulating layer interposed between the first electrode and the second electrode; and
a second insulating layer interposed between the first insulating layer and the second electrode, and
wherein a slope of the inclined sidewall changes at a boundary between the first insulating layer and the second insulating layer.