US 12,356,869 B2
Hall integrated sensor and corresponding manufacturing process
Carsten Schmidt, Avezzano (IT); Gerhard Spitzlsperger, Avezzano (IT); and Daniel Hohnloser, Avezzano (IT)
Assigned to LFOUNDRY S.R.L., Avezzano (IT)
Appl. No. 17/625,634
Filed by LFOUNDRY S.R.L., Avezzano (IT)
PCT Filed Jul. 8, 2020, PCT No. PCT/IB2020/056427
§ 371(c)(1), (2) Date Jan. 7, 2022,
PCT Pub. No. WO2021/005532, PCT Pub. Date Jan. 14, 2021.
Claims priority of application No. 19185046 (EP), filed on Jul. 8, 2019.
Prior Publication US 2022/0246840 A1, Aug. 4, 2022
Int. Cl. H10N 52/00 (2023.01); G01R 33/00 (2006.01); G01R 33/07 (2006.01); H10N 52/01 (2023.01); H10N 52/80 (2023.01)
CPC H10N 52/101 (2023.02) [G01R 33/0017 (2013.01); G01R 33/0052 (2013.01); G01R 33/077 (2013.01); H10N 52/01 (2023.02); H10N 52/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated Hall sensor, comprising:
a main wafer of semiconductor material having a substrate with a first surface and a second surface, opposite to the first surface along a vertical axis;
Hall sensor terminals arranged on at least one of the first and second surfaces of the substrate;
an isolation structure in the substrate defining a Hall sensor plate of the integrated Hall sensor, the Hall sensor terminals being arranged internally to the isolation structure,
wherein the integrated Hall sensor further comprises at least one test and calibration coil integrated in the main wafer, having a plurality of windings formed, at least in part, by metal portions arranged above the first and second surfaces of the substrate and defining an inner volume entirely enclosing the Hall sensor plate,
wherein said test and calibration coil comprises:
at least a first metal portion defined in a metal layer formed on a first dielectric layer structure arranged on the first surface of the substrate;
at least a second metal portion defined in a respective metal layer formed on a second dielectric layer structure arranged on the second surface of the substrate; and
at least a through silicon via extending from the second surface to the first surface of the substrate, and
wherein at least one first outer dielectric layer is arranged on the first dielectric structure and said main wafer is attached with the top surface of said outer dielectric layer onto a second wafer, said second wafer being configured for thinning said main wafer from said second surface preferably to a thickness in the range of 10 to 50 micrometers.