US 12,356,867 B2
Semiconductor structure and method of manufacture
Chia-Hua Lin, New Taipei (TW); and Yao-Wen Chang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Jun. 10, 2022, as Appl. No. 17/837,370.
Prior Publication US 2023/0413682 A1, Dec. 21, 2023
Int. Cl. H10N 50/80 (2023.01); G11C 11/16 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01)
CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a bottom electrode;
a magnetic tunneling junction stack over the bottom electrode;
a top electrode over the magnetic tunneling junction stack;
a first dielectric layer covered by the bottom electrode; and
a second dielectric layer under the first dielectric layer, wherein:
the first dielectric layer has a first chemical bond energy,
the second dielectric layer has a second chemical bond energy, and
the first chemical bond energy is at least two times the second chemical bond energy.