US 12,356,813 B2
Electro-optical device having digital-to-analog conversion circuit and electronic apparatus
Hitoshi Ota, Shiojiri (JP)
Assigned to SEIKO EPSON CORPORATION, Tokyo (JP)
Filed by SEIKO EPSON CORPORATION, Tokyo (JP)
Filed on Apr. 25, 2022, as Appl. No. 17/727,945.
Claims priority of application No. 2021-074104 (JP), filed on Apr. 26, 2021.
Prior Publication US 2022/0344444 A1, Oct. 27, 2022
Int. Cl. H01L 27/32 (2006.01); G09G 3/32 (2016.01); G09G 3/3291 (2016.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); G09G 3/3233 (2016.01)
CPC H10K 59/131 (2023.02) [G09G 3/32 (2013.01); G09G 3/3291 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/027 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An electro-optical device comprising:
a display element provided corresponding to an intersection of a data line and a scanning line; and
a Digital-to-Analog (DA) conversion circuit, wherein
the DA conversion circuit includes:
a first DA conversion circuit configured to convert upper two or more bits among a plurality of bits into a first gradation voltage corresponding to the upper two or more bits, and apply the first gradation voltage to the data line;
a second DA conversion circuit configured to convert a part or all of the bits excluding the upper two or more bits among the plurality of bits into a second gradation voltage that reflects the part or all of the bits excluding the upper two or more bits; and
a coupling capacitance including one end electrically coupled to the second DA conversion circuit and another end electrically coupled to the data line,
the first DA conversion circuit includes an upper capacitance element portion including a first capacitance element and a second capacitance element corresponding to each of the upper two or more bits,
the first capacitance element and the second capacitance element are arranged in a direction along the data line,
the second DA conversion circuit includes a lower capacitance element portion including a third capacitance element and a fourth capacitance element corresponding to each of the part or all of the bits excluding the upper two or more bits, and
the third capacitance element and the fourth capacitance element are arranged in a direction along the data line.