US 12,356,748 B2
Solid-state imaging device and electronic apparatus
Yusuke Matsumura, Kanagawa (JP); Takashi Machida, Kanagawa (JP); Hideo Kido, Kanagawa (JP); Ryo Fukui, Kanagawa (JP); and Yu Shiihara, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/755,841
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 17, 2020, PCT No. PCT/JP2020/042691
§ 371(c)(1), (2) Date May 10, 2022,
PCT Pub. No. WO2021/100675, PCT Pub. Date May 27, 2021.
Claims priority of application No. 2019-207923 (JP), filed on Nov. 18, 2019.
Prior Publication US 2022/0415945 A1, Dec. 29, 2022
Int. Cl. H10F 39/00 (2025.01); H04N 25/77 (2023.01); H10F 39/18 (2025.01)
CPC H10F 39/8057 (2025.01) [H04N 25/77 (2023.01); H10F 39/802 (2025.01); H10F 39/18 (2025.01); H10F 39/80373 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A solid-state imaging device, comprising:
a light-receiving surface;
a plurality of pixels that includes a first pixel and a second pixel, wherein each pixel of the plurality of pixels includes a photoelectric conversion section configured to:
photoelectrically convert light incident through the light-receiving surface; and
transfer charges based on the photoelectric conversion of the light;
a separation section configured to electrically and optically separate the photoelectric conversion section of the first pixel from the photoelectric conversion section of the second pixel,
wherein each pixel of the plurality of pixels further includes:
a charge-holding section configured to hold thecharges transferred from the photoelectric conversion section;
a transfer transistor that includes a vertical gate electrode, wherein
the vertical gate electrode reaches the photoelectric conversion section, and
the transfer transistor is configured to transfer the charges from the photoelectric conversion section to the charge-holding section; and
a light-blocking section in a layer between the photoelectric conversion section and the charge-holding section;
a coupling section; and
a plurality of vertical gate electrodes that includes the vertical gate electrode, wherein
vertical gate electrodes of the plurality of vertical gate electrodes are electrically coupled in a plurality of first pixels among the plurality of pixels,
pixels in the plurality of first pixels are adjacent,
the plurality of first pixels shares the coupling section,
the coupling section is in contact with the plurality of vertical gate electrodes,
the coupling section is configured to electrically couple the plurality of vertical gate electrodes, and
in the plurality of first pixels that includes the first pixel and the second pixel:
the vertical gate electrode in the first pixel is opposite to the vertical gate electrode in the second pixel,
the separation section is between the vertical gate electrode of the first pixel and the vertical gate electrode of the second pixel,
the plurality of vertical gate electrodes is in contact with the separation section, and
the coupling section is in contact with a top of the separation section and a top of each of the plurality of vertical gate electrodes.