US 12,356,742 B2
Chip packaging structure and chip packaging method
You-Wei Chang, Taipei (TW); Chien-Chen Lee, Taipei (TW); and Li-Chun Hung, Taipei (TW)
Assigned to TONG HSING ELECTRONIC INDUSTRIES, LTD., Taipei (TW)
Filed by TONG HSING ELECTRONIC INDUSTRIES, LTD., Taipei (TW)
Filed on Oct. 18, 2022, as Appl. No. 17/968,112.
Claims priority of application No. 111134197 (TW), filed on Sep. 8, 2022.
Prior Publication US 2024/0088179 A1, Mar. 14, 2024
Int. Cl. H10F 39/00 (2025.01)
CPC H10F 39/804 (2025.01) [H10F 39/011 (2025.01); H10F 39/811 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A chip packaging structure comprising:
a first substrate;
an image sensing chip disposed on an upper surface of the first substrate, wherein the image sensing chip has an image sensing region;
a supporting member disposed on an upper surface of the image sensing chip and surrounding the image sensing region, wherein the supporting member is formed by stacking a plurality of microstructures with each other, so that the supporting member has a plurality of pores;
a second substrate disposed on an upper surface of the supporting member, wherein the second substrate, the supporting member, and the image sensing chip define an air cavity; and
an encapsulant attached to the upper surface of the first substrate and a side surface of the second substrate, wherein the encapsulant is filled into the plurality of pores of the supporting member.