| CPC H10F 39/80373 (2025.01) [H10F 39/182 (2025.01); H10F 39/8023 (2025.01); H10F 39/807 (2025.01)] | 41 Claims |
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1. A pixel array, comprising:
a plurality of pixel circuits arranged into rows and columns, wherein a first pixel circuit of the plurality of pixel circuits includes:
first, second, third, and fourth photodiodes disposed in a semiconductor material and configured to photogenerate charge in response to incident light;
first, second, third, and fourth transfer transistors coupled to the first, second, third, and fourth photodiodes, respectively;
first and second split floating diffusions disposed in the semiconductor material, wherein the first split floating diffusion is coupled to receive the charge photogenerated by the first and third photodiodes through the first and third transfer transistors, respectively, wherein the second split floating diffusion is coupled to receive the charge photogenerated by the second and fourth photodiodes through the second and fourth transfer transistors, respectively; and
first, second, third, and fourth shared gate structures, wherein the first shared gate structure comprises a gate of the first transfer transistor of the first pixel circuit and a gate of a first transfer transistor of a second pixel circuit of the plurality of pixel circuits, wherein the third shared gate structure comprises a gate of the third transfer transistor of the first pixel circuit and a gate of a third transfer transistor of the second pixel circuit, wherein the second shared gate structure comprises a gate of the second transfer transistor of the first pixel circuit and a gate of a second transfer transistor of a third pixel circuit of the plurality of pixel circuits, wherein the fourth shared gate structure comprises a gate of the fourth transfer transistor of the first pixel circuit and a gate of a fourth transfer transistor of the third pixel circuit.
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