| CPC H10F 39/8037 (2025.01) [H10F 30/225 (2025.01); H10F 39/803 (2025.01); H10F 39/809 (2025.01); H10F 39/807 (2025.01)] | 19 Claims |

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1. A pixel of a pixel array, the pixel comprising:
isolation walls forming sides of the pixel and extending at least partially through a semiconductor substrate of the pixel array between a top surface of the pixel array and a light gathering surface of the pixel array opposite the top surface;
shallow trench isolation material extending from the top surface at least partially into the semiconductor substrate, wherein the shallow trench isolation material separates a first region of the pixel, a second region of the pixel, and a third region of the pixel;
a single-photon avalanche diode (SPAD) comprising:
a cathode layer adjacent to the top surface; and
an anode layer within the semiconductor substrate and adjoining a side of the cathode layer opposite the top surface; and
a control transistor adjacent to the top surface and electrically connected with the SPAD, wherein:
the control transistor is a first control transistor;
the pixel further comprises a second control transistor;
the first control transistor is a gating transistor formed within the third region;
the second control transistor is a quenching transistor electrically connected to the SPAD and formed within the first region; and
the anode layer and the cathode layer of the SPAD are formed at least partially in the second region.
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