US 12,356,729 B2
Snapback electrostatic discharge (ESD) circuit, system and method of forming the same
Chia-Lin Hsu, Hsinchu (TW); Yu-Hung Yeh, Hsinchu (TW); Yu-Ti Su, Hsinchu (TW); and Wun-Jie Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 7, 2021, as Appl. No. 17/143,407.
Claims priority of provisional application 63/000,611, filed on Mar. 27, 2020.
Prior Publication US 2021/0305235 A1, Sep. 30, 2021
Int. Cl. H10D 89/60 (2025.01); H02H 9/04 (2006.01); H10D 30/60 (2025.01)
CPC H10D 89/815 (2025.01) [H02H 9/046 (2013.01); H10D 30/603 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A snapback electrostatic discharge (ESD) protection circuit comprising:
a first well in a substrate, the first well having a first dopant type;
a drain region of a transistor, the drain region being in the first well, and having a second dopant type different from the first dopant type;
a source region of the transistor, the source region being in the first well, having the second dopant type, and being separated from the drain region in a first direction;
a gate region of the transistor, the gate region being over the first well and the substrate;
a second well embedded in the first well, and adjacent to a portion of the drain region, and the second well having the second dopant type;
a third well embedded in the first well, the third well having the second dopant type, and being adjacent to a portion of the source region, a top surface of the third well is coplanar with a top surface of the first well and a top surface of the source region; and
a first shallow trench isolation (STI) region adjacent to the drain region of the transistor, and being in the second well;
wherein the first well has a first depth in a second direction different from the first direction; and
the second well has a second depth in the second direction, and the second depth is equal to the first depth.