| CPC H10D 89/811 (2025.01) [H10D 30/603 (2025.01); H10D 30/65 (2025.01)] | 16 Claims |
|
1. A semiconductor device, comprising:
a P-type body region and an N-type drift region disposed in a substrate;
a gate electrode disposed on the P-type body region and the N-type drift region and comprising a high concentration doping region and a high resistance region, wherein a dopant concentration of the high concentration doping region is higher than a dopant concentration of the high resistance region;
a gate silicide film formed adjacent to a silicide blocking insulating film and disposed on the gate electrode so as to vertically overlap the high concentration doping region and the high resistance region,
wherein the gate silicide film is formed on an entire upper surface of the high concentration doping region and a portion of an upper surface of the high resistance region, such that the high resistance region passes through an interface between the gate silicide film and the silicide blocking insulating film and extends to an interface between the high concentration doping region and the high resistance region;
a highly doped source region disposed in the P-type body region;
a highly doped drain region disposed in the N-type drift region;
a first spacer on one sidewall of the gate electrode and adjacent to the highly doped source region, and a second spacer on the other sidewall of the gate electrode and adjacent to the highly doped drain region,
wherein the silicide blocking insulating film comprises a first portion on an upper surface of the gate electrode, a second portion on the second spacer, and a third portion on the N-type drift region and in direct contact with a gate insulating film;
a P-type buried layer abutting the P-type body region, having a different dopant concentration than the P-type body region, and disposed below the N-type drift region; and
an N-type buried layer disposed below the P-type buried layer and the P-type body region,
wherein the gate silicide film vertically overlaps the P-type body region, the N-type drift region and the P-type buried layer,
wherein the high concentration doping region is in contact with the P-type body region and the N-type drift region via the gate insulating film, and the high resistance region is in contact with the N-type drift region via the gate insulating film, and
wherein the interface between the high concentration doping region and the high resistance region is spaced apart from the interface between the gate silicide film and the silicide blocking insulating film.
|