US 12,356,726 B2
Semiconductor devices and methods of manufacturing the same
Sungok Lee, Osan-si (KR); Sangdo Park, Yongin-si (KR); Jun Seomun, Seoul (KR); and Bonghyun Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 30, 2023, as Appl. No. 18/192,712.
Application 18/192,712 is a continuation of application No. 16/946,620, filed on Jun. 30, 2020, granted, now 11,646,305.
Claims priority of application No. 10-2019-0122523 (KR), filed on Oct. 2, 2019; and application No. 10-2020-0007272 (KR), filed on Jan. 20, 2020.
Prior Publication US 2023/0246017 A1, Aug. 3, 2023
Int. Cl. H01L 27/02 (2006.01); H10D 89/10 (2025.01)
CPC H10D 89/10 (2025.01) 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming active regions on a substrate including a standard cell region that includes standard cells and a filler cell region that includes a filler cell, wherein the filler cell is between a first standard cell and a second standard cell of the standard cells;
forming gate lines intersecting the active regions and extending in a first direction that is parallel to an upper surface of the substrate;
forming filler contacts, wherein the filler contacts comprises at least one wiring filler contact that is connected to at least one of the active regions in the filler cell region and extends in the first direction;
forming a via structure in contact with the at least one wiring filler contact in the filler cell region; and
forming a lower wiring pattern in contact with an upper surface of the via structure in the filler cell region and extending into the standard cell region in a second direction intersecting the first direction,
wherein the at least one wiring filler contact is above the substrate and is below the lower wiring pattern.