US 12,356,724 B2
Double-sided integrated circuit die and integrated circuit package including the same
Myeong-Eun Hwang, Seoul (KR); and In Suh Hwang, Seoul (KR)
Assigned to Myeong-Eun Hwang, Seoul (KR)
Filed by Myeong-Eun Hwang, Seoul (KR)
Filed on Sep. 27, 2024, as Appl. No. 18/900,415.
Claims priority of application No. 10-2023-0151896 (KR), filed on Nov. 8, 2023.
Prior Publication US 2025/0151411 A1, May 8, 2025
Int. Cl. H10D 88/00 (2025.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H10D 88/101 (2025.01) [H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An integrated circuit die comprising:
a substrate including a front side and a back side opposite to the front side;
a front structure including a first element layer on the front side of the substrate and a first wiring layer on the first element layer;
a back structure including a second element layer on the back side of the substrate and a second wiring layer on the second element layer; and
at least one vertical interconnector penetrating through the substrate, the first element layer and the first wiring layer, or penetrating through the substrate, the second element layer, and the second wiring layer,
wherein the first element layer includes at least one semiconductor element having an active region defined in a region adjacent to the front side within the substrate,
wherein the second element layer includes at least one semiconductor element having an active region defined in a region adjacent to the back side within the substrate, and
wherein each of the front structure and the back structure constitutes an integrated circuit device with different structures and functions.