CPC H10D 86/60 (2025.01) [H05K 1/189 (2013.01); H10D 86/441 (2025.01); H05K 2201/10128 (2013.01)] | 18 Claims |
1. An array substrate comprising a first region and a second region, wherein the second region is distributed around the first region, the second region comprises a binding region adjacent to the first region in a first direction, and the binding region comprises:
a driving chip binding region and a flexible printed circuit binding region, wherein the driving chip binding region is distributed in the binding region, and the flexible printed circuit binding region is distributed on two sides of the driving chip binding region in a second direction intersecting with the first direction,
wherein the driving chip binding region comprises a first pad, a wiring region and a second pad sequentially distributed in the first direction, wherein the first pad is arranged close to the first region, and the first pad comprises a plurality of first solder joints arranged side by side along the second direction, and wherein the second pad comprises a second solder joint group and an isolation region, the second solder joint group is located on two sides of the isolation region in the second direction, and the second solder joint group comprises a plurality of second solder joints arranged side by side along the second direction;
the second solder joints of the second solder joint group are connected to the flexible printed circuit binding region through wires, and the wires pass through the wiring region.
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