US 12,356,718 B2
Display substrate, display device and manufacturing method of the display substrate
Xiaona Liu, Beijing (CN); Jianjun Wang, Beijing (CN); and Weitao Chen, Beijing (CN)
Assigned to BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/779,193
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 29, 2021, PCT No. PCT/CN2021/103056
§ 371(c)(1), (2) Date May 24, 2022,
PCT Pub. No. WO2023/272480, PCT Pub. Date Jan. 5, 2023.
Prior Publication US 2024/0170496 A1, May 23, 2024
Int. Cl. H10D 86/60 (2025.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H10D 86/021 (2025.01); H10D 86/441 (2025.01); H10D 86/451 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A display substrate, comprising a base substrate, and a gate electrode layer, a gate insulation layer, an active layer and a source/drain metal layer laminated one on another on the base substrate, wherein the display substrate further comprises a first insulation layer, a first electrode layer, a second insulation layer and a second electrode layer laminated one on another, the first insulation layer is located at a side of the source/drain metal layer away from the base substrate, a via hole is formed in the second insulation layer, and the first electrode layer is electrically coupled to the source/drain metal layer through the via hole;
wherein the second electrode layer comprises a connection member, an orthogonal projection of the connection member onto the base substrate covers an orthogonal projection of the via hole onto the base substrate, and the connection member is electrically coupled to the source/drain metal layer and the first electrode layer;
wherein a plurality of gate lines arranged parallel to each other in a first direction and a plurality of data lines arranged parallel to each other in a second direction are formed on the base substrate, a minimum region enclosed by two adjacent gate lines and two adjacent data lines is a pixel region, the second electrode layer comprises a hollowed-out region, an orthogonal projection of the hollowed-out region onto the base substrate is located in the pixel region, the hollowed-out region comprises a plurality of hollowed-out patterns arranged parallel to each other in a third direction, the first direction is perpendicular to the second direction, and the third direction intersects the first direction and the second direction;
wherein the hollowed-out pattern comprises a body member and a corner member, and the corner member is located on at least one of two sides of the pixel region close to the data line;
wherein each pixel region comprises a first chip region and a second chip region arranged in the second direction, and the corner member of the hollowed-out pattern in the first chip region and the corner member of the hollowed-out pattern in the second chip region are arranged at sides of the pixel region close to different data lines respectively.