| CPC H10D 86/60 (2025.01) [H10D 86/021 (2025.01); H10D 86/451 (2025.01)] | 20 Claims |
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1. An array substrate, comprising:
a substrate;
an oxide semiconductor layer disposed on the substrate, comprising a channel region and conductive regions located at both sides of the channel region;
a gate insulating layer disposed on a side of the oxide semiconductor layer away from the substrate;
a gate electrode disposed on a side of the gate insulating layer away from the substrate;
an interlayer insulating layer disposed on a side of the gate electrode away from the substrate; and
a source-drain electrode metal layer disposed on a side of the interlayer insulating layer away from the substrate, and electrically connected to the conductive regions through via holes penetrating the interlayer insulating layer;
wherein edges of the gate insulating layer are respectively overlapped with the conductive regions on the both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate; and
wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second insulating layer, the first interlayer insulating layer is located at a side surface of the second insulating layer close to the substrate, and the gate electrode and the gate insulating layer are exposed from the first interlayer insulating layer.
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