| CPC H10D 84/907 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/975 (2025.01)] | 11 Claims |
|
1. A semiconductor integrated circuit device comprising a plurality of cell rows each having a plurality of standard cells arranged in a first direction, wherein:
a first cell row, as one of the plurality of cell rows, includes a first standard cell having a logical function and a second standard cell having no logical function placed at at least one of both ends of the first cell row,
the first standard cell includes:
a first region that is a region for formation of a transistor of a first conductivity type,
a second region that is a region for formation of a transistor of a second conductivity type different from the first conductivity type and is adjacent to the first region in a second direction perpendicular to the first direction,
a first nanosheet extending in the first direction, formed in the first region,
a second nanosheet extending in the first direction, formed in the second region,
a first gate interconnect extending in the second direction, surrounding a periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions, and
a second gate interconnect extending in the second direction, surrounding a periphery of the second nanosheet in the second and third directions,
the second standard cell includes:
a third nanosheet extending in the first direction, formed at the same position as the first nanosheet in the second direction,
a fourth nanosheet extending in the first direction, formed at the same position as the second nanosheet in the second direction,
a first dummy gate interconnect extending in the second direction, surrounding a periphery of the third nanosheet in the second and third directions, and
a second dummy gate interconnect extending in the second direction, surrounding a periphery of the fourth nanosheet in the second and third directions,
in a first cross section cutting the first gate interconnect by a first plane defined by the second and third directions along the second direction, a face of the first nanosheet on a first side that is one side in the second direction is exposed from the first gate interconnect,
in a second cross section cutting the second gate interconnect by a second plane defined by the second and third directions along the second direction, a face of the second nanosheet on a second side that is one side in the second direction is exposed from the second gate interconnect,
in a third cross section cutting the first dummy gate interconnect by a third plane defined by the second and third directions along the second direction, a face of the third nanosheet on the first side in the second direction is exposed from the first dummy gate interconnect, and
in a fourth cross section cutting the second dummy gate interconnect by a fourth plane defined by the second and third directions along the second direction, a face of the fourth nanosheet on the second side in the second direction is exposed from the second dummy gate interconnect.
|