US 12,356,711 B2
Late gate extension
Ruilong Xie, Niskayuna, NY (US); Christopher J Waskiewicz, Rexford, NY (US); Jay William Strane, Warwick, NY (US); Hemanth Jagannathan, Niskayuna, NY (US); and Brent Anderson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,545.
Prior Publication US 2023/0139379 A1, May 4, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/63 (2025.01); H10D 62/151 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A vertical field-effect transistor (VFET) device, comprising:
at least one bottom source/drain region present on a substrate;
at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device;
a gate stack alongside the at least one fin;
a gate extension metal adjacent to the gate stack at a base of the at least one fin;
a barrier layer that separates the gate extension metal from the gate stack, wherein the barrier layer is a conductive material; and
at least one top source/drain region at a top of the at least one fin.