| CPC H10D 84/853 (2025.01) [H01L 21/02293 (2013.01); H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H10D 30/0245 (2025.01); H10D 30/6211 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] | 20 Claims | 

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               1. A structure, comprising: 
            a substrate; 
                a first fin located in a first region of the structure for n-type transistors, the first fin extending from a first portion of the substrate; 
                a second fin located in a second region of the structure for p-type transistors, the second fin extending from a second portion of the substrate, wherein the second fin includes a top portion over a bottom portion, the first fin and the bottom portion of the second fin include crystalline silicon, the top portion of the second fin includes a semiconductor material that has a higher charge carrier mobility than silicon, a top surface of the second fin and a top surface of the first fin are substantially coplanar, and the bottom portion of the second fin extends deeper than the first fin towards the substrate, wherein the top portion of the second fin and the bottom portion of the second fin have substantially same width, wherein the first fin is wider than the second fin, wherein a top surface of the substrate has a first slope that gradually extends downward from the first region to the second region; and 
                an isolation structure disposed on sidewalls of the first and second fins, wherein a top surface of the isolation structure has a second slope that gradually extends downward from the first region to the second region. 
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