US 12,356,685 B2
Looped long channel field-effect transistor
Ruilong Xie, Niskayuna, NY (US); Ardasheir Rahman, Schenectady, NY (US); Hemanth Jagannathan, Niskayuna, NY (US); Robert Robison, Rexford, NY (US); Brent Anderson, Jericho, VT (US); and Heng Wu, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 28, 2021, as Appl. No. 17/486,911.
Prior Publication US 2023/0101235 A1, Mar. 30, 2023
Int. Cl. H10D 62/17 (2025.01); H01L 21/76 (2006.01); H10D 30/60 (2025.01); H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/299 (2025.01) [H01L 21/76 (2013.01); H10D 30/611 (2025.01); H10D 30/63 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01); H10D 84/016 (2025.01); H10D 84/038 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first source/drain region;
a second source/drain region;
an isolation region between and electrically isolating the first source/drain region and the second source/drain region, wherein the first source/drain region and the second source/drain region directly contact opposing vertical side walls of the isolation region;
a channel having a first end adjoining the first source/drain region and a second end adjoining the second source/drain region such that the first source/drain region and the second source/drain region separate the opposing vertical side walls of the isolation region from sides of the channel, wherein the first source/drain region, the second source/drain region, the isolation region and the channel form a closed loop; and
a gate stack adjoining the channel.