US 12,356,681 B2
Semiconductor device and methods of manufacturing
Shahaji B. More, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Mar. 11, 2022, as Appl. No. 17/654,517.
Prior Publication US 2023/0290822 A1, Sep. 14, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/118 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of nanostructure channels over a substrate,
wherein the plurality of nanostructure channels are arranged in a direction perpendicular to the substrate;
a gate structure wrapping around the plurality of nanostructure channels over the substrate;
a source/drain region adjacent to the plurality of nanostructure channels and the gate structure;
an inner spacer layer disposed between a top surface of a mesa region and a bottom nanostructure channel of the plurality of nanostructure channels; and
a buffer region under the source/drain region,
wherein a curved top surface of the buffer region includes an apex height that is greater relative to a height of a bottom surface of the inner spacer layer, and
wherein the apex height of the curved top surface is lesser relative to a height of a top surface of the inner spacer layer,
wherein a first distance, between the bottom surface of the inner spacer layer and a top surface of a top nanostructure channel, is less relative to a second distance, between the bottom surface of the inner spacer layer and a bottom depth of the buffer region.
 
7. A semiconductor device, comprising:
a bottom nanostructure channel over a substrate;
a first hybrid fin structure adjacent to a first side of the bottom nanostructure channel;
a second hybrid fin structure adjacent to a second side of the bottom nanostructure channel that is opposite the first side; and
a buffer region between the first hybrid fin structure and the second hybrid fin structure,
wherein a first portion of the buffer region extends into a first shallow trench isolation region between the first side of the bottom nanostructure channel and the first hybrid fin structure,
wherein a second portion of the buffer region extends into a second shallow trench isolation region that is between the second side of the bottom nanostructure channel and the second hybrid fin structure, and
wherein a curved top surface of the buffer region includes an apex height that is greater relative to a height of a top surface of the first shallow trench isolation region, greater relative to a height of a top surface of the second shallow trench isolation region, and lesser relative to a height of a bottom surface of the bottom nanostructure channel.
 
14. A semiconductor device, comprising:
a bottom nanostructure channel over a substrate;
a plurality of hybrid fin structures, including a first hybrid fin structure and a second hybrid fin structure, adjacent to the bottom nanostructure channel; and
a buffer region between the first hybrid fin structure and the second hybrid fin structure,
wherein at least one of:
a first portion of the buffer region extends into a first shallow trench isolation region between the bottom nanostructure channel and the first hybrid fin structure, or
a second portion of the buffer region extends into a second shallow trench isolation region that is between the bottom nanostructure channel and the second hybrid fin structure.