| CPC H10D 48/362 (2025.01) [H10D 62/151 (2025.01); H10D 62/235 (2025.01)] | 19 Claims |
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1. A planar transistor device comprising a gate having a gate length that extends in a gate length direction and a gate width that extends in a gate width direction, the transistor comprising:
a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface;
a gate cap on the gate structure;
a channel region;
a source region;
a drain region; and
a plurality of layers of a two-dimensional (2D) material in a vertically stacked layer and positioned in at least one of the source region and the drain region, wherein the at least one layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the at least one layer of 2D material in the gate length direction and across an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the at least one layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate wherein an uppermost layer of the plurality of layers of 2D material in the source region and an uppermost layer of the plurality of layers of 2D material in the drain region are substantially co-planar with an upper surface of the gate cap; and
wherein the gate structure is positioned on a substantially planar upper surface of the semiconductor substrate and wherein the at least one layer of 2D material is positioned across an entirety of the source region and across an entirety of the drain region, wherein a portion of the semiconductor substrate positioned below the gate structure comprises the channel region and wherein the channel region is substantially free of the of the at least one layer of 2D material.
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