US 12,356,674 B2
Method for fabricating a strained structure and structure formed
Tsung-Lin Lee, Hsinchu (TW); Chih-Hao Chang, Chu-Bei (TW); Chih-Hsin Ko, Fongshan (TW); Feng Yuan, Yonghe (TW); and Jeff J. Xu, Jhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 29, 2023, as Appl. No. 18/522,461.
Application 16/711,497 is a division of application No. 15/425,552, filed on Feb. 6, 2017, granted, now 10,510,887, issued on Dec. 17, 2019.
Application 18/522,461 is a continuation of application No. 17/671,042, filed on Feb. 14, 2022, granted, now 11,855,210.
Application 17/671,042 is a continuation of application No. 16/986,043, filed on Aug. 5, 2020, granted, now 11,251,303, issued on Feb. 15, 2022.
Application 16/986,043 is a continuation of application No. 16/711,497, filed on Dec. 12, 2019, granted, now 10,998,442, issued on May 4, 2021.
Application 15/425,552 is a continuation of application No. 14/844,247, filed on Sep. 3, 2015, granted, now 9,564,529, issued on Feb. 7, 2017.
Application 14/844,247 is a continuation of application No. 13/910,633, filed on Jun. 5, 2013, granted, now 9,147,594, issued on Sep. 29, 2015.
Application 13/910,633 is a continuation of application No. 12/775,006, filed on May 6, 2010, granted, now 8,497,528, issued on Jul. 30, 2013.
Prior Publication US 2024/0097034 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/69 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/31 (2006.01); H01L 21/311 (2006.01); H01L 21/76 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 62/832 (2025.01)
CPC H10D 30/797 (2025.01) [H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 21/02636 (2013.01); H01L 21/30604 (2013.01); H01L 21/31 (2013.01); H01L 21/31116 (2013.01); H01L 21/76 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 62/152 (2025.01); H10D 62/156 (2025.01); H10D 62/822 (2025.01); H10D 64/015 (2025.01); H10D 64/018 (2025.01); H10D 62/8325 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor protrusion disposed on a substrate;
a gate structure disposed over the semiconductor protrusion;
a dielectric isolation structure; and
a source/drain feature associated with the semiconductor protrusion, the source/drain feature including:
a dielectric layer that includes a first portion in direct contact with a sidewall of the semiconductor protrusion and a second portion in direct contact with a sidewall of the dielectric isolation structure; and
a first strained layer disposed on the semiconductor protrusion and is prevented from interfacing with the sidewall of the semiconductor protrusion and the sidewall of the dielectric isolation structure by the first and second portions of the dielectric layer, respectively, the first strained layer having a bottom surface facing the substrate that is in direct contact with a portion of the semiconductor protrusion defined by the substrate.