US 12,356,672 B2
Semiconductor device
Yutaka Okazaki, Kanagawa (JP); Akihisa Shimomura, Kanagawa (JP); Naoto Yamade, Kanagawa (JP); Tomoya Takeshita, Kanagawa (JP); and Tetsuhiro Tanaka, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Dec. 1, 2023, as Appl. No. 18/526,315.
Application 18/526,315 is a continuation of application No. 17/861,432, filed on Jul. 11, 2022, granted, now 12,046,683.
Application 17/861,432 is a continuation of application No. 17/006,987, filed on Aug. 31, 2020, granted, now 11,393,930, issued on Jul. 19, 2022.
Application 17/006,987 is a continuation of application No. 16/367,329, filed on Mar. 28, 2019, granted, now 10,763,373, issued on Sep. 1, 2020.
Application 16/367,329 is a continuation of application No. 15/204,015, filed on Jul. 7, 2016, granted, now 10,276,724, issued on Apr. 30, 2019.
Claims priority of application No. 2015-140794 (JP), filed on Jul. 14, 2015.
Prior Publication US 2024/0128380 A1, Apr. 18, 2024
Int. Cl. H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 64/62 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6757 (2025.01) [H10D 30/6706 (2025.01); H10D 30/6734 (2025.01); H10D 30/6739 (2025.01); H10D 30/6755 (2025.01); H10D 64/62 (2025.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 99/00 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor including a first channel formation region;
a second transistor including a second channel formation region;
a third transistor including a third channel formation region;
a capacitor;
a first insulator over the first channel formation region;
a first conductor over the first insulator and overlapping the first channel formation region;
a second insulator over the first conductor;
a second conductor and a third conductor over the second insulator;
a third insulator over the second conductor and the third conductor;
a fourth conductor overlapping the second channel formation region;
a fifth conductor overlapping the third channel formation region;
a fourth insulator over the fourth conductor and the fifth conductor;
a sixth conductor over the fourth insulator;
a fifth insulator over the sixth conductor; and
a seventh conductor over the fifth insulator and overlapping the sixth conductor,
wherein the second channel formation region and the third channel formation region are over the third insulator,
wherein the second channel formation region overlaps the second conductor,
wherein the third channel formation region overlaps the third conductor,
wherein the sixth conductor is configured to be one electrode of the capacitor,
wherein the seventh conductor is configured to be another electrode of the capacitor,
wherein the sixth conductor is electrically connected to the second channel formation region and the third channel formation region,
wherein the sixth conductor is electrically connected to the first conductor,
wherein the first channel formation region includes silicon,
wherein the second channel formation region includes oxide semiconductor, and
wherein the third channel formation region includes oxide semiconductor.