| CPC H10D 30/6757 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6215 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |
|
1. A semiconductor device comprising:
a substrate;
a first active pattern, which extends in a first direction on the substrate;
a second active pattern, which extends in the first direction on the substrate and is spaced apart from the first active pattern by a first pitch in a second direction different from the first direction;
a third active pattern, which extends in the first direction on the substrate and is spaced apart from the second active pattern by a second pitch greater than the first pitch in the second direction;
a field insulating layer, which borders side walls of each of the first to third active patterns;
a dam, which is between the first active pattern and the second active pattern on the field insulating layer, the dam having an upper surface including a first portion and a second portion;
a gate electrode, which extends in the second direction, and has a first portion on the first active pattern, a second portion on the second active pattern, and a third portion on the third active pattern;
a first work function layer disposed between the first portion of the gate electrode and the dam and covering the first portion different from the second portion of the upper surface of the dam; and
a second work function layer disposed between the second portion of the gate electrode and the dam and covering the second portion different from the first portion of the upper surface the dam.
|