| CPC H10D 30/6735 (2025.01) [H10D 30/014 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/118 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0128 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] | 20 Claims |
|
17. A semiconductor device comprising:
a first semiconductor fin and a second semiconductor fin disposed over a semiconductor substrate;
an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin;
a wall fin disposed on the isolation insulating layer;
a gate structure disposed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin;
a first source/drain epitaxial layer disposed over a source/drain region of the first semiconductor fin and a second source/drain epitaxial layer disposed over a source/drain region of the second semiconductor fin; and
a first fin liner layer disposed on a bottom part of the first source/drain epitaxial layer, and a second fin liner layer disposed on a bottom part of the second source/drain epitaxial layer,
wherein the first source/drain epitaxial layer and the second source/drain epitaxial layer are separated by the wall fin,
the wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer,
the first, second, and third dielectric layers are made of different materials from each other,
the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers, and
a fourth dielectric layer different from the first, second, and third dielectric layers is disposed in direct contact with the third dielectric layer and the gate structure as viewed in top view.
|