US 12,356,667 B2
Separate epitaxy layers for nanowire stack GAA device
Tung Ying Lee, Hsinchu (TW); Kai-Tai Chang, Kaohsiung (TW); and Meng-Hsuan Hsiao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 11, 2023, as Appl. No. 18/220,397.
Application 17/346,378 is a division of application No. 16/536,113, filed on Aug. 8, 2019, granted, now 11,038,036, issued on Jun. 15, 2021.
Application 18/220,397 is a continuation of application No. 17/346,378, filed on Jun. 14, 2021, granted, now 11,742,405.
Claims priority of provisional application 62/736,962, filed on Sep. 26, 2018.
Prior Publication US 2023/0352551 A1, Nov. 2, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 10/01 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H01L 21/02433 (2013.01); H10D 10/054 (2025.01); H10D 64/018 (2025.01); H10D 84/0158 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate including a first substrate region;
a first plurality of strips of a first semiconductor material over the first substrate region;
a semiconductor base layer between the first plurality of strips and the substrate, the semiconductor base layer having a flat upper surface;
a first gate structure surrounding at least a first strip of the first plurality of strips, the semiconductor base layer being distinct from the first gate structure;
an isolation region along opposing sides of the semiconductor base layer; and
a first source/drain structure contacting the first plurality of strips.