| CPC H10D 30/6735 (2025.01) [H10D 64/258 (2025.01); H10D 84/0135 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 30/62 (2025.01)] | 18 Claims |
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1. A transistor device comprising:
a substrate;
a lower transistor comprising a lower gate, a lower channel region on the substrate, lower insulating spacers on sidewalls of the lower gate, and a lower source/drain region;
an upper transistor comprising an upper gate, an upper channel region, upper insulating spacers on sidewalls of the upper gate, and an upper source/drain region, wherein the lower transistor is between the upper transistor and the substrate; and
an isolation region that separates the lower insulating spacers from the upper insulating spacers, the isolation region comprising a first portion that separates the lower channel region from the upper channel region and a second portion that separates the lower source/drain region from the upper source/drain region,
wherein the lower gate of the lower transistor contacts the upper gate of the upper transistor, and
wherein the first portion of the isolation region has a first thickness that is less than or equal to a second thickness of the second portion of the isolation region.
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