US 12,356,664 B2
Device and method of fabricating multigate devices having different channel configurations
Tsung-Lin Lee, Hsinchu (TW); Choh Fei Yeap, Hsinchu (TW); Da-Wen Lin, Taipei (TW); and Chih Yeh, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 2, 2021, as Appl. No. 17/465,300.
Claims priority of provisional application 63/199,841, filed on Jan. 28, 2021.
Prior Publication US 2022/0238678 A1, Jul. 28, 2022
Int. Cl. H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
epitaxially growing a stack of alternating layers of a first semiconductor layer and a second semiconductor layer on a substrate wherein the stack extends from a first region to a second region, wherein at least two of the first semiconductor layers of the stack of alternating layers extend from a first region of the substrate to the second region of the substrate, and wherein the epitaxially growing provides the at least two of the first semiconductor layers have a constant thickness from the first region to the second region;
patterning the stack of alternating layers to form a first fin structure extending from the substrate in the first region and a second fin structure each extending from the substrate in the second region;
forming a first gate-all-around (GAA) transistor on the first fin structure, wherein the first GAA transistor has a channel region within a first plurality of nanostructures, wherein the first plurality of nanostructures includes the at least two of the first semiconductor layers; and
forming a second GAA transistor on the second fin structure, wherein the second GAA transistor has a second channel region configuration, wherein the second GAA transistor has a channel region within a second plurality of nanostructures, wherein the second plurality of nanostructures includes the at least two of the first semiconductor layers, and wherein the second plurality of nanostructures is less than the first plurality of nanostructures.