| CPC H10D 30/6729 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active pattern on a substrate;
a source/drain pattern on the active pattern;
a channel pattern connected to the source/drain pattern;
a gate electrode on the channel pattern;
a gate insulating layer interposed between the channel pattern and the gate electrode;
an active contact on the source/drain pattern;
a first lower interconnection line on the active contact;
a second lower interconnection line provided on the gate electrode and disposed at a level the same as that of the first lower interconnection line;
a first spacer between the gate electrode and the active contact; and
a second spacer spaced apart from the first spacer with the gate electrode or the active contact interposed therebetween,
wherein the gate electrode comprises an electrode body portion and an electrode protruding portion, which protrudes from a top surface of the electrode body portion and is in contact with a bottom surface of the second lower interconnection line,
the active contact comprises a contact body portion and a contact protruding portion, which protrudes from a top surface of the contact body portion and is in contact with a bottom surface of the first lower interconnection line,
the second spacer is separated from the gate electrode by the gate insulating layer, and
a top surface of the first spacer is higher than a top surface of the second spacer.
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