US 12,356,659 B2
Semiconductor device
Doohyun Lee, Hwaseong-si (KR); Heonjong Shin, Yongin-si (KR); Hyunho Park, Suwon-si (KR); Minchan Gwak, Hwaseong-si (KR); Seon-Bae Kim, Hwaseong-si (KR); and Jinyoung Park, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 8, 2022, as Appl. No. 17/834,987.
Claims priority of application No. 10-2021-0130652 (KR), filed on Oct. 1, 2021.
Prior Publication US 2023/0115743 A1, Apr. 13, 2023
Int. Cl. H01L 29/786 (2006.01); H10D 30/67 (2025.01)
CPC H10D 30/6713 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate including a first active region and a second active region;
a first active pattern and a second active pattern on the first active region and the second active region, respectively;
a first source/drain pattern and a second source/drain pattern on the first active pattern and the second active pattern, respectively;
a first silicide pattern and a second silicide pattern on the first source/drain pattern and the second source/drain pattern, respectively, a first thickness of the first silicide pattern being greater than a second thickness of the second silicide pattern; and
a first active contact and a second active contact coupled to the first source/drain pattern and the second active pattern, respectively, a lowermost portion of the first active contact being at a higher level than a lowermost portion of the second active contact,
wherein a low onion of the first silicide pattern is at a lower level than an uppermost portion of the first active pattern.