| CPC H10D 30/0215 (2025.01) [H01L 21/764 (2013.01); H01L 21/76897 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 64/015 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 30/0212 (2025.01); H10D 30/6735 (2025.01); H10D 84/0151 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a semiconductor fin over a substrate;
an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein the epitaxial S/D feature includes a top surface, a first sidewall, and a second sidewall opposing the first sidewall;
a dielectric layer and a dielectric fin over the substrate, wherein each of the dielectric layer and the dielectric fin has a respective topmost portion below the top surface of the epitaxial S/D feature, wherein the first sidewall of the epitaxial S/D feature is facing the dielectric layer and the second sidewall of the epitaxial S/D feature is facing the dielectric fin, and wherein the dielectric layer and the dielectric fin have different material compositions; and
an S/D contact disposed on the epitaxial S/D feature, wherein the S/D contact partially covers the top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature, and wherein the S/D contact is in contact with the dielectric layer and free of contact with the dielectric fin.
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11. A semiconductor device, comprising:
a fin protruding from a substrate;
a dielectric layer and a dielectric fin over the substrate and sandwiching the fin, wherein the dielectric layer is lower than the dielectric fin;
an epitaxial feature disposed over the fin and between the dielectric layer and the dielectric fin;
an air gap stacked between the epitaxial feature and the dielectric fin; and
a conductive feature disposed over the epitaxial feature, wherein the conductive feature is in contact with a top surface of the epitaxial feature, a sidewall of the epitaxial feature that is facing the dielectric layer, and the dielectric layer, wherein the conductive feature is spaced apart from the dielectric fin, and wherein the top surface of the epitaxial feature is above topmost portions of both the dielectric layer and the dielectric fin.
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18. A semiconductor device, comprising:
a plurality of channel layers suspended over a substrate;
an epitaxial feature abutting the plurality of channel layers;
a first dielectric layer over the substrate and facing a first sidewall of the epitaxial feature;
a second dielectric layer over the substrate and facing a second sidewall of the epitaxial feature, wherein a top surface of the first dielectric layer is below a top surface of the second dielectric layer, and wherein each of the top surface of the first dielectric layer and the top surface of the second dielectric layer is below a topmost portion of the epitaxial feature; and
a conductive feature disposed over the epitaxial feature and in contact with the first sidewall of the epitaxial feature, wherein the conductive feature is free of contact with the second sidewall of the epitaxial feature.
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