| CPC H10D 1/665 (2025.01) [H01L 23/3157 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H10D 1/047 (2025.01); H10D 1/692 (2025.01)] | 20 Claims |
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1. An integrated circuit (IC), comprising:
a first insulating layer comprising a first metal interconnect structure stacked above a bottom die;
a substrate disposed above the first insulating layer;
a second metal interconnect structure disposed above the substrate;
a through-substrate via (TSV) directly connecting the first metal interconnect structure to the second metal interconnect structure, wherein a width of the TSV covers the first insulating layer; and
a stacked deep trench capacitor (DTC) structure disposed in the substrate comprising a first plurality of trenches extending from a first side of the substrate, and a second plurality of trenches extending from a second side of the substrate;
wherein the first plurality of trenches includes a first group of trenches and a second group of trenches, wherein an outermost edge of the first group of trenches and an outermost edge of the second group of trenches nearest to the outermost edge of the first group of trenches are spaced apart from one another by a first distance, and wherein each of the first group of trenches and the second group of trenches comprise a plurality of trenches that are spaced from one another by a second distance smaller than the first distance; and
wherein the DTC structure includes an inner electrode, an outer electrode, and a dielectric layer that extend continuously from over the first group of trenches to over the second group of trenches, the dielectric layer separating the inner electrode from the outer electrode.
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