| CPC H10D 1/043 (2025.01) [H10D 1/042 (2025.01); H10D 1/692 (2025.01); H10D 1/716 (2025.01)] | 7 Claims |

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1. A method of fabricating a metal-insulator-metal (MIM) capacitor comprising:
providing a dielectric layer;
forming a hardmask layer on an upper surface of the dielectric layer;
forming a plurality of mandrel lines on the upper surface of the hardmask layer;
forming a conformal layer over the plurality of mandrel lines and the hardmask layer;
etching portions of the conformal layer from top portions of the plurality of mandrel lines and from any portion of the hardmask layer that is exposed, wherein other portions of the conformal layer that remain on the hardmask layer form a plurality of spacers;
removing the plurality of mandrel lines;
forming a non-conformal layer on top portions of the plurality of spacers and on portions of the hardmask layer which are located outward relative to the plurality of spacers;
etching portions of the hardmask layer located between the plurality of spacers;
etching portions of the dielectric layer located between the plurality of spacers to form a plurality of trenches in the dielectric layer;
removing the hardmask layer from the dielectric layer;
forming a bottom capacitor plate over the upper surface of the dielectric layer, the bottom capacitor plate including the plurality of trenches defined therein, wherein the plurality of trenches are configured to provide a desired capacitance density of the MIM capacitor;
providing a top capacitor plate; and
disposing a capacitor insulating layer between the top and bottom capacitor plates and within the plurality of trenches.
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