US 12,356,637 B2
Method for forming semiconductor structure and semiconductor structure
Lingxiang Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Aug. 25, 2021, as Appl. No. 17/411,108.
Application 17/411,108 is a continuation of application No. PCT/CN2021/098929, filed on Jun. 8, 2021.
Claims priority of application No. 202010814732.X (CN), filed on Aug. 13, 2020.
Prior Publication US 2022/0052151 A1, Feb. 17, 2022
Int. Cl. H10B 12/00 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01)
CPC H10D 1/043 (2025.01) [H10B 12/0335 (2023.02); H10B 12/31 (2023.02); H10D 1/696 (2025.01); H10D 1/716 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method for forming semiconductor structure, comprising the following steps:
providing a semiconductor substrate, which at least comprises discrete conducting layers in the semiconductor substrate;
forming discretely arranged supporting structures on the semiconductor substrate, lower portions of the supporting structures comprising bottom conducting layers, wherein a width of each one of the bottom conducting layers is less than or equal to ⅓ of a width of each one of the multiple supporting structures in a direction parallel to a top surface of the semiconductor substrate, capacitor openings being comprised between the supporting structures, and the bottom conducting layers being electrically connected with the conducting layers;
forming lower electrodes only on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layers;
forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and
forming an upper electrode covering the capacitor dielectric layer, to form a capacitor structure.