US 12,356,634 B2
Phase change memory
Paolo Giuseppe Cappelletti, Seveso (IT); Fausto Piazza, Grenoble (FR); and Andrea Redaelli, Milan (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Jul. 27, 2022, as Appl. No. 17/874,595.
Claims priority of application No. 2108320 (FR), filed on Jul. 30, 2021.
Prior Publication US 2023/0032898 A1, Feb. 2, 2023
Int. Cl. H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/80 (2023.02) [H10B 63/30 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a substrate including a semiconductor region and an insulating region;
a first insulating layer over the substrate;
first and second conductive vias crossing the first insulating layer;
a phase change material layer resting on the first insulating layer; and
an interconnection network covering the phase change material layer and first insulating layer and including a conductive track;
wherein a first end of the first conductive via is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region; and
wherein a first end of the second conductive via is in contact with both the phase change material layer and the conductive track, and wherein a second end of the second conductive via is in contact only with the insulating region.