US 12,356,632 B2
Memory device and preparing method thereof
Xiaoguang Wang, Hefei (CN); Dinggui Zeng, Hefei (CN); Huihui Li, Hefei (CN); and Kanyu Cao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Jun. 23, 2022, as Appl. No. 17/808,396.
Application 17/808,396 is a continuation of application No. PCT/CN2022/078533, filed on Mar. 1, 2022.
Claims priority of application No. 202111007065.5 (CN), filed on Aug. 30, 2021.
Prior Publication US 2023/0065326 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10D 30/67 (2025.01)
CPC H10B 61/22 (2023.02) [H10D 30/6728 (2025.01); H10D 30/6755 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate,
a plurality of memory cells disposed in an array on the substrate, the array comprising a plurality of rows extending in a row direction and a plurality of columns extending in a column direction, wherein:
the row direction is parallel to a first direction defined by extension of gate word lines, the column direction is parallel to a second direction defined by extension of bit lines, and the second direction intersects the first direction;
the plurality of memory cells in adjacent rows are staggered in the row direction, such that a distance between two adjacent memory cells in any row is a first distance (D1); and
the plurality of memory cells in adjacent columns are staggered in the column direction, such that a staggered distance (D2) between memory cells in adjacent columns is less than the first distance; and
the bit lines disposed in the second direction, wherein the bit lines are located above the plurality of memory cells, and each of the bit lines is correspondingly connected to the memory cells on two adjacent columns; and
a common source line disposed between the substrate and the memory cells.