| CPC H10B 51/30 (2023.02) [G11C 11/223 (2013.01); H01L 28/57 (2013.01); H01L 28/60 (2013.01); H10B 51/10 (2023.02); H10B 53/00 (2023.02); H10B 53/30 (2023.02)] | 20 Claims |

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1. A semiconductor device, comprising:
a random access memory (RAM) structure over a substrate, the RAM structure comprising:
a bottom electrode layer;
a ferroelectric layer over the bottom electrode layer; and
a top electrode layer over the ferroelectric layer; and
wherein from the cross-sectional view,
a top surface of the top electrode has a recessed region, and
a bottom of the recessed region is in a position higher than a top surface of the ferroelectric layer and a top surface of the bottom electrode;
a dielectric layer over the substrate and laterally surrounding a lower portion of the RAM structure, wherein from a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a first vertical portion, and the first vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer, and the bottom electrode layer of the RAM structure non-overlaps the dielectric layer,
the ferroelectric layer wraps around three sides of the first vertical portion of the bottom electrode layer.
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