US 12,356,629 B2
Semiconductor memory devices and methods of manufacturing thereof
Meng-Han Lin, New Taipei (TW); and Chia-En Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 30, 2023, as Appl. No. 18/325,766.
Application 18/325,766 is a continuation of application No. 17/232,734, filed on Apr. 16, 2021, granted, now 11,696,449.
Prior Publication US 2023/0309316 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 51/30 (2023.01); H10B 51/20 (2023.01); H10B 51/40 (2023.01); H10B 51/50 (2023.01)
CPC H10B 51/30 (2023.02) [H10B 51/20 (2023.02); H10B 51/40 (2023.02); H10B 51/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die, comprising:
a device portion, comprising:
an array of active memory devices, each row of the array of active memory devices extending in a first direction; and
at least one interface portion located adjacent to an axial end of the device portion in the first direction, the at least one interface portion having a staircase profile in a vertical direction, the at least one interface portion comprising:
an array of gate vias, each row of the array of gate vias extending in the first direction and located parallel to a row of an array of dummy memory devices in a second direction perpendicular to the first direction, each gate via being electrically coupled to one or more interface vias of a corresponding one of the dummy memory devices located adjacent thereto.