US 12,356,622 B2
Nonvolatile semiconductor memory device and method for manufacturing same
Yoshiaki Fukuzumi, Yokohama (JP); Ryota Katsumata, Yokohama (JP); Masaru Kito, Yokohama (JP); Masaru Kidoh, Tokyo (JP); Hiroyasu Tanaka, Tokyo (JP); Yosuke Komori, Yokohama (JP); Megumi Ishiduki, Yokohama (JP); Junya Matsunami, Yokohama (JP); Tomoko Fujiwara, Yokohama (JP); Hideaki Aochi, Kawasaki (JP); Ryouhei Kirisawa, Yokohama (JP); Yoshimasa Mikajiri, Yokohama (JP); and Shigeto Oota, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Sep. 12, 2023, as Appl. No. 18/465,223.
Application 18/465,223 is a continuation of application No. 17/576,164, filed on Jan. 14, 2022, granted, now 11,792,992.
Application 17/576,164 is a continuation of application No. 16/849,457, filed on Apr. 15, 2020, granted, now 11,257,842, issued on Feb. 22, 2022.
Application 16/849,457 is a continuation of application No. 16/519,705, filed on Jul. 23, 2019, granted, now 10,658,383, issued on May 19, 2020.
Application 16/519,705 is a continuation of application No. 15/915,653, filed on Mar. 8, 2018, granted, now 10,418,378, issued on Sep. 17, 2019.
Application 15/915,653 is a continuation of application No. 15/424,532, filed on Feb. 3, 2017, granted, now 9,941,296, issued on Apr. 10, 2018.
Application 15/424,532 is a continuation of application No. 15/064,270, filed on Mar. 8, 2016, granted, now 9,601,503, issued on Mar. 21, 2017.
Application 15/064,270 is a continuation of application No. 14/833,827, filed on Aug. 24, 2015, granted, now 9,318,503, issued on Apr. 19, 2016.
Application 14/833,827 is a continuation of application No. 14/150,504, filed on Jan. 8, 2014, granted, now 9,312,134, issued on Apr. 12, 2016.
Application 14/150,504 is a continuation of application No. 12/724,713, filed on Mar. 16, 2010, granted, now 8,653,582, issued on Feb. 18, 2014.
Claims priority of application No. 2009-072950 (JP), filed on Mar. 24, 2009.
Prior Publication US 2024/0008276 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/223 (2006.01); H01L 21/265 (2006.01); H10B 43/20 (2023.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 30/69 (2025.01); H10D 62/17 (2025.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 64/66 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 21/223 (2013.01); H01L 21/265 (2013.01); H10B 43/20 (2023.02); H10D 30/025 (2025.01); H10D 30/0413 (2025.01); H10D 30/63 (2025.01); H10D 30/69 (2025.01); H10D 30/693 (2025.01); H10D 30/696 (2025.01); H10D 62/292 (2025.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 64/661 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device, comprising:
a layer-stack including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction;
a first insulating layer provided in the first direction on an uppermost electrode layer included in the layer-stack;
a first semiconductor pillar extending through at least a part of the layer-stack in the first direction, the first semiconductor pillar having an annular shape when viewed from the first direction;
a first insulating film provided inside the first semiconductor pillar;
a first semiconductor layer in contact with the first semiconductor pillar, a lower end of the first semiconductor layer being located below an upper end of the first insulating film; and
a first metal plug electrically contacting with the first semiconductor pillar via the first semiconductor layer.