US 12,356,618 B2
Semiconductor device and method of manufacturing the same
Ki Hong Lee, Gyeonggi-do (KR); Seung Ho Pyi, Gyeonggi-do (KR); and Seung Jun Lee, Seoul (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 15, 2022, as Appl. No. 17/672,462.
Application 17/672,462 is a continuation of application No. 17/202,683, filed on Mar. 16, 2021, granted, now 11,690,224.
Application 17/202,683 is a continuation of application No. 16/363,659, filed on Mar. 25, 2019, granted, now 10,978,472, issued on Apr. 13, 2021.
Application 16/363,659 is a continuation of application No. 14/282,898, filed on May 20, 2014, granted, now 10,283,518, issued on May 7, 2019.
Claims priority of application No. 10-2013-0152591 (KR), filed on Dec. 9, 2013.
Prior Publication US 2022/0173122 A1, Jun. 2, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01)
CPC H10B 43/27 (2023.02) [H10B 43/40 (2023.02); H10D 30/025 (2025.01); H10D 30/0413 (2025.01); H10D 30/693 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first stacked structure including a first semiconductor pattern, a first conductive layer and a first insulating layer, the first conductive layer and the first insulating layer stacked along a sidewall of the first semiconductor pattern;
a second stacked structure including a second semiconductor pattern, a second conductive layer and a second insulating layer, the second conductive layer and the second insulating layer stacked along a sidewall of the second semiconductor pattern, the second conductive layer and the second insulating layer stacked in a direction in which the first conductive layer and the first insulating layer are stacked;
a third insulating layer including a coupling pattern, and interposed between the first stacked structure and the second stacked structure; and
a multilayer dielectric layer surrounding each of the first semiconductor pattern and the second semiconductor pattern,
wherein a portion of the multilayer dielectric layer surrounding the first semiconductor pattern extends to be in contact with the second semiconductor pattern,
wherein the third insulating layer contacts the first insulating layer and the second insulating layer,
wherein the coupling pattern couples the first semiconductor pattern to the second semiconductor pattern,
wherein the sidewall of the first semiconductor pattern includes a first outer portion and a second outer portion facing opposite directions, and
wherein the coupling pattern extends to cover a lower part of the first outer portion and does not extend to cover a lower part of the second outer portion.