US 12,356,616 B2
Openings layout of three-dimensional memory device
Jia He, Wuhan (CN); Haihui Huang, Wuhan (CN); Fandong Liu, Wuhan (CN); Yaohua Yang, Wuhan (CN); Peizhen Hong, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Zongliang Huo, Wuhan (CN); Yaobin Feng, Wuhan (CN); Baoyou Chen, Wuhan (CN); and Qingchen Cao, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 8, 2023, as Appl. No. 18/534,480.
Application 17/017,417 is a division of application No. 16/046,475, filed on Jul. 26, 2018, granted, now 10,804,283, issued on Oct. 13, 2020.
Application 17/017,417 is a division of application No. PCT/CN2018/077716, filed on Mar. 1, 2018.
Application 18/534,480 is a continuation of application No. 18/156,619, filed on Jan. 19, 2023, granted, now 11,903,195.
Application 18/156,619 is a continuation of application No. 17/017,417, filed on Sep. 10, 2020, granted, now 11,574,919, issued on Feb. 7, 2023.
Claims priority of application No. 201710134033.9 (CN), filed on Mar. 7, 2017.
Prior Publication US 2024/0107757 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H10B 43/20 (2023.02) [H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/0413 (2025.01); H10D 30/69 (2025.01); H10D 64/037 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a stack structure comprising conductor layers and insulating layers stacking alternately; and
an array of semiconductor channels located in a first region of the stack structure, wherein each of the array of semiconductor channels extends through the stack structure, and wherein:
the array of semiconductor channels comprises:
semiconductor channels in a first row and adjacent to a second region of the stack structure, wherein the second region is adjacent to the first region; and
semiconductor channels in a second row further away from the second region than the semiconductor channels in the first row;
the semiconductor channels in the first row have a substantially same size and have an oval cross section, the semiconductor channels in the second row have a substantially same size and have a circular cross section;
a first semiconductor channel in the first row has a first distance L1 from a second semiconductor channel in the second row and adjacent to the first semiconductor channel;
the second semiconductor channel has a second distance L2 from a third semiconductor channel in a third row and adjacent to the second semiconductor channel;
the third semiconductor channel has a third distance L3 from a fourth semiconductor channel in a fourth row and adjacent to the third semiconductor channel;
the fourth semiconductor channel has a fourth distance L4 from a fifth semiconductor channel in a fifth row and adjacent to the fourth semiconductor channel; and
L1>L2>L3>L4.